The present invention relates to a variable gain amplifier for use in an AGC circuit or the like.
When a demodulator in a communication apparatus, for example, demodulates a received signal, the received signal is controlled so as to make the signal level of the received signal as constant as possible and then inputted to the demodulator. Thus making the signal level constant improves reliability in demodulation. Also, adjusting the signal to an appropriate level improves the SN ratio (signal-to-noise ratio) and prevents signal distortion due to saturation, so that reliability in demodulation can be improved also in these respects. Conventionally, an AGC (Automatic Gain Control) circuit is used to make the signal level of a received signal constant. As is well known, the AGC circuit is formed by a variable gain amplifier.
Such a variable gain amplifier is required to amplify a signal at a low level with a high SN ratio and amplify a signal at a high level without causing distortion due to saturation. In order to satisfy these conditions contrary to each other at the same time, a conventional technique is known which uses a combination of a first amplifier circuit having good noise characteristics and a high gain and a second amplifier circuit having a high input saturation level and a low gain.
FIG. 5 is a block diagram showing an example of this type of conventional variable gain amplifier.
A variable gain amplifier 102 shown in FIG. 5 includes a first amplifier circuit 104 having good noise characteristics and a high gain and a second amplifier circuit 106 having a high input saturation level and a low gain. A signal S10 is inputted commonly to the first and second amplifier circuits 104 and 106. Output signals S11 and S12 of the first and second amplifier circuits 104 and 106 are combined with each other for output by a combiner 108.
When the gain of the variable gain amplifier 102 is to be increased, the combiner 108 provides a relatively large weight to the output signal S11 of the first amplifier circuit 104 on the basis of a gain control signal S5 and then adds the two output signals S11 and S12 to each other. As a result, the output signal of the combiner 108, that is, an output signal S13 of the variable gain amplifier 102, reflects the output signal of the first amplifier circuit 104 more strongly. Thus, the gain of the variable gain amplifier 102 is increased. On the other hand, when the gain of the variable gain amplifier 102 is to be decreased, the combiner 108 provides a relatively small weight to the output signal S11 of the first amplifier circuit 104 and then adds the two output signals S11 and S12 to each other. As a result, the output signal S13 of the variable gain amplifier 102 reflects the output signal of the second amplifier circuit 106 more strongly. Thus, the gain of the variable gain amplifier 102 is decreased.
In FIG. 5, the output signal S13 of the variable gain amplifier 102 is inputted to a variable gain amplifier 10 in a second stage so that the level of the signal is further controlled. Therefore, the overall gain is changed more, and thus the level of the signal is controlled in a wider range. Of course, it is possible to connect another variable gain amplifier subsequent to the variable gain amplifier 110.
FIG. 6 is a circuit diagram showing in detail the variable gain amplifier 102 of FIG. 5.
As shown in FIG. 6, the first amplifier circuit 104 is formed by a first differential amplifier circuit 112 including transistors Q1 and Q2, a constant current source 10, resistances R1 and R2 and the like. The second amplifier circuit 106 is formed by a second differential amplifier circuit 114 including transistors Q3 and Q4, a constant current source 11, resistances R3 and R4 and the like.
Bases of the transistors Q1 and Q2 forming the first differential amplifier circuit 112 arc connected to input terminals IN and INB, respectively, and emitters of the transistors Q1 and Q2 are both connected to one end of a current path 116. The resistances R1 and R2 are load resistances of the transistors Q1 and Q2, and one end of each of the resistances is connected to a positive power supply Vcc. Another end of the current path 116 is connected to a ground, and the constant current source 10 is inserted at a midpoint on the current path 116.
Bases of the transistors Q3 and Q4 forming the second differential amplifier circuit 114 are connected to input terminals IN and INB, respectively, and emitters of the transistors Q3 and Q4 are both connected to one end of a current path 118 via a resistance RE. The resistances R3 and R4 are load resistances of the transistors Q3 and Q4, and one end of each of the resistances is connected to the power supply Vcc. Another end of the current path 118 is connected to the ground, and the constant current source 11 is inserted at a midpoint on the current path 118.
The combiner 108 is formed by transistors Q5 to Q12, resistances RS1 and RS2, a voltage source Vb, and a variable voltage source Vc. The pairs of transistors Q5 and Q6, transistors Q7 and Q8, transistors Q9 and Q10, and transistors Q11 and Q12 have emitters connected to collectors of the transistors Q1 to Q4, respectively. Collectors of the transistors Q5, Q8, Q9, and Q12 are connected to the other ends of the resistances R1, R2, R3, and R4, respectively. Collectors of the transistors Q6, Q7, Q10, and Q11 are connected to the power supply Vcc.
Bases of the transistors Q6, Q7, Q9, and Q12 are each connected to a cathode of the voltage source Vb, and bases of the transistors Q5, Q8, Q10, and Q11 are each connected to a cathode of the variable voltage source Vc. An anode of the variable voltage source Vc is connected to the cathode of the voltage source Vb, and an anode of the voltage source Vb is connected to the ground. The two resistances RS1 and RS2 are connected between the collectors of the transistors Q5 and Q9 and between the collectors of the transistors Q8 and Q12, respectively.
The collectors of the transistors Q5 and Q8 are connected to output terminals OUTB and OUT of the variable gain amplifier 102, respectively. With such a configuration, when the voltage of the variable voltage source Vc is controlled by a gain control signal SG (corresponding to S5 in FIG. 5) to set the voltage of the variable voltage source to a sufficiently high positive value, for example, the transistors Q5, Q8, Q10, and Q11 are brought into an on state, and the transistors Q6, Q7, Q9, and Q12 are brought into an off state. Therefore, the output signals of the second differential amplifier circuit 114 outputted from the collectors of the transistors Q3 and Q4 are blocked by the transistors Q9 and Q12, so that the output signals of the second differential amplifier circuit are not added to the output signals of the first differential amplifier circuit 112 via the resistances RS1 and RS2. Thus, only the output signals of the first differential amplifier circuit 112 are outputted from the output terminals OUTB and OUT via the transistors Q5 and Q8.
On the other hand, when the voltage of the variable voltage source Vc is set to a negative value of a sufficiently high magnitude, the transistors Q5, Q8, Q10, and QI1 are brought into an off state, and the transistors Q6, Q7, Q9, and Q12 are brought into an on state. Therefore, the output signals of the first differential amplifier circuit 112 outputted from the collectors of the transistors Q1 and Q2 are blocked by the transistors Q5 and Q8, so that the output signals of the first differential amplifier circuit art not added to the output signals of the second differential amplifier circuit 114 supplied via the resistances RS1 and RS2. Thus, only the output signals of the second differential amplifier circuit 114 are outputted from the output terminals OUTB and OUT.
When the voltage of the variable voltage source Vc is set to an intermediate voltage, the collector currents of the transistors Q5, Q8, Q9, and Q12 have current values corresponding to the voltage of the variable voltage source Vc. Accordingly, the output signals of the first and second differential amplifier circuits 112 and 114 are subjected to weighted addition corresponding to the voltage of the variable voltage source, and the results are outputted from the output terminals OUTB and OUT. As the voltage of the variable voltage source Vc is increased, the weight given to the output signals of the first differential amplifier circuit 112 becomes larger, and hence signals that reflect the output signals of the first differential amplifier circuit 112 more strongly are outputted from the output terminals OUTB and OUT.
The first differential amplifier circuit 112 has a higher gain than the second differential amplifier circuit 114. Hence, as the voltage of the variable voltage source Vc is increased, the gain of the variable gain amplifier 102 is increased, while as the voltage of the variable voltage source Vc is decreased, the gain of the variable gain amplifier 102 is decreased.
Since the emitters of the transistors Q1 and Q2 are connected directly to each other and no emitter resistance is inserted, resistance thermal noise does not occur in the first differential amplifier circuit 112, so that the first differential amplifier circuit 112 has a good SN ratio. On the other hand, the second differential amplifier circuit 114 has the emitter resistances RE connected to the transistors Q3 and Q4. Although the second differential amplifier circuit 114 has a low SN ratio, the second differential amplifier circuit 114 has a higher saturation input level than the first differential amplifier circuit 112.
Thus, the variable gain amplifier 102 provides a good SN ratio when the gain of the variable gain amplifier 102 is increased, whereas the variable gain amplifier 102 has a higher saturation input level to prevent or reduce signal distortion when the gain of the variable gain amplifier 102 is decreased.
Whatever magnitude the gain set in the conventional variable gain amplifier 102 described above has, the constant current sources 10 and 11 feed the current paths 116 and 118 with constant currents as bias currents of the first and second differential amplifier circuits 112 and 114 at all times. In this respect, there is room for a reduction of power consumption. The reduction of power consumption of an electronic apparatus, such as a communication apparatus, and is an important challenge to be dealt with constantly simultaneously with the reduction of the size and weight of the apparatus.